Sorav Bansal

Sorav Bansal's Homepage

Associate Professor,
Microsoft Chair Professor,
Department of Computer Science,
IIT Delhi.
sbansal at

Chief Technology Officer and Co-Founder

Brief Bio

Sorav Bansal is an Associate Professor and Microsoft Chair Professor at the CS department at IIT Delhi, and works in the areas of programming languages and operating systems. His primary research interests involve investigating superoptimization-based compiler design. Sorav obtained his B.Tech. from IIT Delhi, and Ph.D. from Stanford University.

If you are passionate about system software building or want to participate in high-impact systems research targeted for new emerging markets, join our research & development team at COMPILER.AI.

We work at the intersection of compilers and formal verification, and so a background in these areas would be great --- but as long as you enjoy hacking together interesting software systems, this prior experience is not necessary and can be learned quickly once you are on board with us. We welcome applications from PhD, Masters, and Bachelors degree holders. We would love to talk to you if you already have research experience in compilers/systems.

You will be an early founding member of the team with a great deal of responsibility, and we can assure you that you will have a lot of fun working with us. We offer competitive salaries and attractive equity in the company for our early team members. Our early team members will form our founding team! If you are interested, please reach out to me over email. You can also visit COMPILER.AI for more details. [Growing Our Team Flyer]



Here are the courses I am teaching in the current semester. See all my courses here. See Compiler Design/Optimization lecture videos here
See OS lecture videos here
See our conference talks and other research videos here

Social Media

Running Systems

Source Code Repositories

Current PhD Students

Graduated PhD Students

Representative Publications

(see full publication list at
With each paper, I also provide an informal summary/comment to provide some context on the paper.

We are working on an optimizing C compiler based on program synthesis and superoptimization techniques. Towards this, we have developed a black-box equivalence checker, and these papers describe some of the problems we solved in the process, and our current results. More details on the early part of this work are also available in Manjeet Dahiya's PhD thesis. If you are interested in exploring further, please check our project page.
[ ASPLOS 2019 ] HawkEye: Efficient Fine-grained OS Support for Huge Pages [ slides, lightning talk ]
This paper discusses simple yet effective algorithms for huge-page management in the OS kernel. The primary ideas are: access-coverage based huge-page promotion, asynchronous page pre-zeroing, exploring the notion of fairness in dealing with huge-page allocations, and the effect of using hardware performance counters to estimate the benefits of huge-page allocations. The ideas are evaluated over a wide range of workloads for several metrics.
[ TPDS 2017 ] The Unicorn Runtime: Efficient distributed shared memory programming for hybrid CPU-GPU clusters
How can a programmer harness the combined computing power of CPUs and GPUs in a computing cluster without dealing with all the nitty gritties of the underlying system and its optimizations? The paper presents an intuitive programming model (which is perhaps not entirely new). The contribution of the paper is in algorithms to automatically map a program written in this programming model on a cluster of CPUs and GPUs through compile-time and run-time support in a system called Unicorn.

[ SOSP 2013 ] Fast Dynamic Binary Translation for the Kernel [ talk video ]
Dynamic binary translation (DBT) is a technique with a wide variety of applications; innovative ways to employ DBT appear almost regularly in the research literature. This paper explains how to perform DBT for an OS kernel efficiently even in the presence of high rates of interrupt and exception activity. The capability of turning DBT on and off during system execution is quite cool, and did not exist in any previous DBT system. The orchestration of translated instructions in the processor's instruction cache to improve the performance of the system (i.e., the translated system can be faster than the native system) is quite interesting. We use our DBT implementation to monitor the sharing behaviour of the Linux kernel.

This was the first SOSP paper ever from India.

[ ASPLOS 2013 ] Efficient Virtualization on Embedded Power Architecture Platforms
I quote one of our ASPLOS 2013 reviewers:

---begin quote---
I find it extremely interesting to observe how a small set of seemingly innocuous architectural differences between Power and x86 leads to completely different "locally optimal" BT virtualization approaches (comparing this approach with the one outlined in the Adams paper [4]). These differences are: x86 has segmentation, Power has software-loaded TLB and variable page sizes, Power has orthogonal rwx page permissions, and x86 has variable length instructions.

It is almost like asking, how would the universe differ if the fine structure constant had a value of 0.00829 instead of 0.00729. Answer: a lot!

For this reason, I think the paper is a very good fit for ASPLOS. Even if architects do their best to think carefully about ramifications of their choices, this paper is an eye opener into a world of, probably, unforeseen consequences. As such, like it very much. And I think it should be a must-read for current and future architects (and not just narrowly from a virtualization point of view).
---end quote---

Thank you dear (anonymous) reviewer for liking our work!

[ OSDI 2008 ] Binary Translation Using Peephole Superoptimizers
Can we automatically infer translations from one architecture to another using synthesis and superoptimization techniques? This paper demonstrates such capability for PowerPC to x86 translation. The performance of the translated code is better than the widely-used commercial Rosetta translator (shipped with Apple's OS X) at that time. The paper provides techniques to dynamically map the state of one machine to the state of another machine in tandem with synthesis-based code generation, for better overall quality of the generated code.

[ ASPLOS 2006 ] Automatic Generation of Peephole Superoptimizers
How to automatically generate a peephole optimizer for x86 using brute-force superoptimization? This paper has received significant attention since it was published. Our current research is targetted towards generalizing and scaling the ideas presented in this paper.

[ FAST 2004 ] CAR: Clock with Adaptive Replacement
This paper extends the well-known CLOCK algorithm for cache replacement (used in most operating systems) with ideas presented in previous work on Adaptive Replacement Cache (ARC). As mentioned on ARC's wikipedia page, variants of this approach have been implemented and deployed in several systems. The primary advantage of CAR (CLOCK with Adaptive Replacement) over ARC is that it gets rid of the LRU lock, while retaining all the benefits of ARC. CAR and its variants are widely used today in a variety of systems. CAR also finds a favourable mention on the Wikipedia page on Page replacement algorithm.